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automotive power data sheet rev. 1.0, 2010-04-12 spoc - BTS6460SF for advanced front light control spi power controller
data sheet 2 rev. 1.0, 2010-04-12 spoc - BTS6460SF table of contents 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1 terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 3 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.1 pin assignment spoc - BTS6460SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 3.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4.2 thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 5 power supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.1 power supply modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5.2 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.3 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.4 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 power stages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.1 output on-state resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.2 input circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 6.3 power stage output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.4 inverse current behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 6.6 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 7 automatic pwm generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.1 pwm setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.2 pwm clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7.3 pwm duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.4 channel phase shift . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 7.5 daisy chain operation with pwm generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 7.6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 7.7 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 8 protection functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.1 over current protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 8.2 over current protection at high v ds . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.3 over current protection for short circuit type 2 protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 8.4 over temperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 8.5 reverse polarity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.6 over voltage protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 8.7 loss of ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.8 loss of v bb . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 8.9 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 8.10 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 9 diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 9.1 diagnosis word at spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.2 load current sense diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 9.3 sense synchronization during automatic pwm generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 9.4 sense measurement without synchronization signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 9 9.5 automatic current sense multiplexer swit ching . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table of contents
spoc - BTS6460SF table of contents data sheet 3 rev. 1.0, 2010-04-12 9.6 switch bypass diagnosis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 9.7 open load in off-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 9.8 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 9.9 command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 10 serial peripheral interface (spi) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.1 spi signal description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 10.2 daisy chain capability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 10.3 timing diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 10.4 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 10.5 spi protocol 16bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 10.6 register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 11 application description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 12 package outlines spoc - BTS6460SF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
pg-dso-36-43 type package marking spoc - BTS6460SF pg-dso-36-43 BTS6460SF data sheet 4 rev. 1.0, 2010-04-12 for advanced front light control spi power controller spoc - BTS6460SF 1overview features ? 16 bit serial peripheral interface for control and diagnosis ? integrated pwm generator ? 3.3 v and 5 v compatible logic pins ? very low stand-by current ? enhanced electromagnet ic compatibility (emc) for bulbs as well as leds with increased slew rate ? stable behavior at under voltage ? device ground independent from load ground ? green product (rohs-compliant) ? aec qualified description the spoc - BTS6460SF is a four channel high-side smart power switch in pg-dso-36-43 package providing embedded protective functions. it is especially designe d to control standard exterior lighting in automotive applications. in order to use the same hardware, the device can be configured to bulb or led mode for channel 2 and channel 3. as a result, both load types are opti mized in terms of switching and diagnosis behavior. it is specially designed to drive exterior lamps up to 65w, 27w and 10w and hidl. product summary operating voltage power switch v bb 4.5 ? 28 v logic supply voltage v dd 3.0?5.5v supply voltage for load dump protection v bb(ld) 40 v maximum stand-by current at 25 c i bb(stb) 4.5 a typical on-state resistance at t j = 25 c channel 0, 1 channel 2, 3 r ds(on,typ) 3.5 m ? 11 m ? maximum on-state resistance at t j = 150 c channel 0, 1 channel 2, 3 r ds(on,max) 9m ? 28 m ? spi access frequency f sclk(max) 5mhz
spoc - BTS6460SF overview data sheet 5 rev. 1.0, 2010-04-12 configuration and status diagnosis ar e done via spi. the spi is daisy chai n capable. the device provides a current sense signal per channel that is multiplexed to th e diagnosis pin is. it can be enabled and disabled via spi commands. an over load and over temperature flag is provided in the spi diagnosi s word. a multiplexed switch bypass monitor provides short-circuit to v bb diagnosis. in off state a current source can be switched to the output of one selected channel in order to detect an open load. additionally, there is an integrated pwm generator im plemented, which allows autonomous pwm operation with programmable phase shifts, duty cycles and pwm frequencie s. the status diagnosis a nd the current sense signal is available for each channel. the spoc - BTS6460SF provides a fail-safe feature via limp home input pin. the power transistors are built by n-channel vertical power mosfets with charge pumps. protective functions ? reverse battery protecti on with external components ? reversave tm - reverse battery protection by self turn on of all channels ? short circuit protection ? over load protection ? thermal shutdown with latch and dynamic temperature sensor ? over current tripping ? over voltage protection ? loss of ground protection ? electrostatic discha rge protection (esd) diagnostic functions ? multiplexed proportional load current sense signal (is) ? enable function for current s ense signal configurable via spi ? high accuracy of current sense signal at wide load current range ? current sense ratio ( k ilis ) configurable for leds or bulbs for channel 2 and 3 ? very fast diagnosis in led mode ? feedback on over temperature and over load via spi ? multiplexed switch bypass monitor provides short circuit to v bb detection ? integrated, in two steps programmable current source for open load in off-state detection application specific functions ? fail-safe activation via lhi pin applications ? high-side power switch for 12 v grounded loads in automotive applications ? especially designed for standard exterior lighting like high beam, low beam, indicator, parking light and equivalent leds ? load type configuration via spi (bulbs or leds) for optimized load control ? replaces electromechanical relays, fuses and discrete circuits
data sheet 6 rev. 1.0, 2010-04-12 spoc - BTS6460SF block diagram 2blockdiagram figure 1 block diagram spoc - BTS6460SF limp home control led mode control 3 2 1 channel 0 power supply driver logic gate control & charge pump clamp for inductive load over current protection load current sense temperature sensor esd protection gnd spi current sense multiplexer so sclk si cs switch bypass monitor vbb out3 out2 out1 out0 in2 in3 in1 pwm generator vdd lhi is s y pclk is
spoc - BTS6460SF block diagram data sheet 7 rev. 1.0, 2010-04-12 2.1 terms figure 2 shows all terms used in this data sheet. figure 2 terms in all tables of electrical characteri stics is valid: channel related symbols without channel number are valid for each channel separately (e.g. v ds specification is valid for v ds0 ? v ds3 ). all spi register bits are marked as follows: addr.parameter (e.g. hwcr.cl ). in spi register description, the values in bold letters (e.g. 0 ) are default values. i dd v dd v so v in2 i si v in3 i cs v bb i is i bb vdd s0 si cs is vbb v si v cs v sclk v in1 i in1 in1 in2 i sclk sclk v is i in3 in3 gnd i gnd v lhi lhi out0 i l0 out1 i l1 out2 i l2 out3 i l3 v out3 v out2 v ds3 v ds2 v out1 v out0 v ds1 v ds0 i so i in2 terms_pwm.emf i lhi pclk i pclk v pclk i issy issy v issy
data sheet 8 rev. 1.0, 2010-04-12 spoc - BTS6460SF pin configuration 3 pin configuration 3.1 pin assignment spoc - BTS6460SF figure 3 pin configuration pg-dso-36-43 (top view) out1 out2 out2 vbb 36 35 34 33 32 31 1 2 3 4 5 6 7 8 30 29 vbb out1 out1 out1 28 27 26 25 24 23 9 10 11 12 13 14 15 16 22 21 test n.c. n.c. gnd 18 19 20 17 in3 out0 out0 out0 out0 in1 in2 vbb vbb gnd lhi cs sclk si out3 out3 vbb test vbb pclk vdd issy so is
spoc - BTS6460SF pin configuration data sheet 9 rev. 1.0, 2010-04-12 3.2 pin definitions and functions pin symbol i/o function power supply pins 1, 2, 9, 28, 35, 36 1) 1) all vbb pins have to be connected. vbb ? positive power supply for high-side power switch 19 vdd ? logic supply (5 v) 15, 22 gnd ? ground connection parallel input pins (integrated pull -down, leave unused pins unconnected) 16 in1 i input signal of channel 1 (high active) 17 in2 i input signal of channel 2 (high active) 18 in3 i input signal of channel 3 (high active) power output pins 3, 4, 5, 6 2) 2) all outputs pins of each channel have to be connected. out0 o protected high-side power output of channel 0 31, 32, 33, 34 2) out1 o protected high-side power output of channel 1 29, 30 2) out2 o protected high-side power output of channel 2 7, 8 2) out3 o protected high-side power output of channel 3 spi, pwm & diagnosis pins 14 cs i chip select of spi interface (low active); integrated pull up 13 sclk i serial clock of spi interface 12 si i serial input of spi interface (high active) 11 so o serial output of spi interface 27 pclk i pwm clock reference signal 21 is o current sense output signal 20 issy o current sense synchronization signal limp home pin (integrated pull-down, pull-down resistor recommended) 10 lhi i limp home activation signal (high active) not connected pins 23, 24 n.c. ? not connected, internally not bonded 25, 26 test ? test pins, internally bonded and pulled down, do not connect
data sheet 10 rev. 1.0, 2010-04-12 spoc - BTS6460SF electrical characteristics 4 electrical characteristics 4.1 absolute maximum ratings absolute maximum ratings 1) t j = -40 to +150 c; all voltages with respect to ground (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max. supply voltage 4.1.1 power supply voltage v bb -0.3 28 v ? 4.1.2 logic supply voltage v dd -0.3 5.5 v ? 4.1.3 reverse polarity voltage according figure 30 -v bat(rev) ?16v t jstart = 25 c t 2min. 2) 4.1.4 supply voltage for short circuit protection (single pulse) v bb(sc) v r ecu = 20 m ? l = 0 or 5 m 3) channel 0, 1 0 24 r cable = 6 m ? /m l cable = 1 h/m channel 2, 3 0 24 r cable = 16 m ? /m l cable = 1 h/m 4.1.5 supply voltage for lo ad dump protection with connected loads v bb(ld) ?40v r i = 2 ? 4) t = 400 ms 4.1.6 current through ground pin i gnd ?25ma t 2min. 4.1.7 current through vdd pin i dd -25 12 ma t 2min. power stages 4.1.8 load current i l -i l(lim) i l(lim) a 5) 4.1.9 maximum energy dissipation single pulse e as mj 6) t j(0) = 150 c channel 0, 1 ? 180 i l(0) = 5 a channel 2, 3 ? 45 i l(0) = 2 a diagnosis pin 4.1.10 current through sense pin is i is -8 8 ma t 2min. input pins 4.1.11 voltage at input pins v in -0.3 5.5 v ? 4.1.12 current through input pins i in -0.75 -2.0 0.75 2.0 ma ? t 2min. spi pins 4.1.13 voltage at chip select pin v cs -0.3 v dd + 0.3 v ? 4.1.14 current through chip select pin i cs -2.0 2.0 ma t 2min. 4.1.15 voltage at serial input pin v si -0.3 v dd + 0.3 v ? 4.1.16 current through serial input pin i si -2.0 2.0 ma t 2min. 4.1.17 voltage at serial clock pin v sclk -0.3 v dd + 0.3 v ? 4.1.18 current through serial clock pin i sclk -2.0 2.0 ma t 2min. 4.1.19 voltage at serial out pin v so -0.3 v dd + 0.3 v ?
spoc - BTS6460SF electrical characteristics data sheet 11 rev. 1.0, 2010-04-12 note: stresses above the ones listed here may cause perm anent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. note: integrated protection functions are designed to prevent ic destruction under fault conditions described in the data sheet. fault conditions are considered as ?outside? normal operating range. protection functions are not designed for continuous repetitive operation. 4.1.20 current through serial output pin so i so -2.0 2.0 ma t 2min. pwm clock and sense synchronization pin 4.1.21 voltage at pwm clock input pin v pclk -0.3 v dd + 0.3 v ? 4.1.22 current through pwm clock input pin i plck -0.75 -2.0 0.75 2.0 ma ? t 2min. 4.1.23 voltage at sense synchronization pin v issy -0.3 v dd + 0.3 v ? 4.1.24 current through se nse synchronization pin i issy -2.0 2.0 ma t 2min. limp home pin 4.1.25 voltage at limp home input pin v lhi -0.3 5.5 v ? 4.1.26 current through limp home input pin i lhi -0.75 -2.0 0.75 2.0 ma ? t 2min. temperatures 4.1.27 junction temperature t j -40 150 c? 4.1.28 dynamic temperature increase while switching ? t j ?60k? 4.1.29 storage temperature t stg -55 150 c? esd susceptibility 4.1.30 esd susceptibility hbm out pins vs. vbb other pins incl. out vs. gnd v esd -4 -2 4 2 kv hbm 7) ? ? 1) not subject to production test, specified by design. 2) device is mounted on an fr4 2s2p board according to jedec jesd51-2,-5,-7 at natu ral convection; the product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board wi th 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). where applicable, a thermal via array under the pa ckage contacted the first inner copper layer. 3) in accordance to aec q100-012 and aec q101-006. 4) r i is the internal resistance of the load dump pulse generator. 5) over current protection is a protection feature. operatio n in over current protection is considered as ?outside? normal operating range. protection features are no t designed for continuous repetitive operation. 6) pulse shape represents inductive switch off: i d(t) = i d (0) (1 - t / t pulse ); 0 < t < t pulse 7) esd resistivity, hbm according to eia/jesd 22-a 114b (1.5 k ? , 100 pf) absolute maximum ratings (cont?d) 1) t j = -40 to +150 c; all voltages with respect to ground (unless otherwise specified) pos. parameter symbol limit values unit conditions min. max.
data sheet 12 rev. 1.0, 2010-04-12 spoc - BTS6460SF electrical characteristics 4.2 thermal resistance note: this thermal data was generated in accordance wit h jedec jesd51 standards. fo r more information, go to www.jedec.org . pos. parameter symbol limit values unit conditions min. typ. max. 4.2.1 junction to soldering point 1) 1) not subject to production test, specified by design. r thjsp ? ? 20 k/w measured to pin 1, 2, 9, 28, 35, 36 4.2.2 junction to ambient 1) r thja ?35?k/w 2) 2) specified r thja values is according to jedec jesd51-2,-5,-7 at natural convection on fr4 2s2p board; the product (chip+package) was simulated on a 76.4 x 114.3 x 1.5 mm board with 2 inner copper layers (2 x 70 m cu, 2 x 35 m cu). where applicable, a thermal via array under the package contacted the first inner copper layer.
spoc - BTS6460SF power supply data sheet 13 rev. 1.0, 2010-04-12 5 power supply the spoc - BTS6460SF is supplied by two supply voltages v bb and v dd . the v bb supply line is used by the power switches. the v dd supply line is used by the spi related circuitr y and for driving the so line. a capacitor between pins vdd and gnd is recommended as shown in figure 30 . there is a power-on reset function implemented for the v dd logic power supply. after start-up of the logic power supply, all spi registers are reset to their default values. the spi interface including da isy chain function is active as soon as v dd is provided in the spec ified range independent of v bb . first spi data are the output register values with ter = 1. specified parameters are valid for the supply voltage range according v bb(nor) or otherwise specified. for the extended supply voltage range according v bb(ext) device functionality (switchi ng, diagnosis and protection functions) are still given, parame ter deviations are possible. 5.1 power supply modes the following table shows all possible power supply modes for v bb , v dd and the pin lhi. 5.1.1 stand-by mode and device wake-up mechanisms stand-by mode is entered as soon as the current sense multiplexer ( dcr.mux ) is in default (stand-by) position, the pwm start bit is reset ( pcr.pst = 0 b ) and all input pins are not set. all error latches are cleared automatically in stand-by mode. as soon as stand-by mode is entered, register hwcr.stb is set. to wake -up the device, the current sense multiplexer ( dcr.mux ) is programmed different to default (s tand-by) position or the pwm start bit is set ( pcr.pst = 1 b ). the power-on wake up time t wu(po) has to be considered for both cases. idle mode parameters are valid, when all channels are switched off, but the current sense multiplexer is not in default position, and v dd supply is available. note: a transition from operation to stand-by mode does not reset the spi registers. so, if v dd is present and spi is programmed, a changing to mux = 111 b does not reset the spi registers. an activation of the channels via the input pin inx will wake up the devic e with the former spi register settings. power supply modes off off spi on reset off on via inx limp home mode without spi normal operation limp home mode with spi 1) 1) spi read only v bb 0v 0v 0v 0v 13.5v 13.5v 13.5v 13.5v 13.5v v dd 0v 0v 5v 5v 0v 0v 0v 5v 5v lhi 0v5v0v5v0v 0v 5v 0v 5v power stage, protection ? ? ? ? ? ? 2) 2) channel 1, 2 and/or 3 activated according to the state of inx ? 2) ?? 2) limp home ? ? ? ? ? ? ? ? ? spi (logic) ? ? ?? reset reset reset ? reset 3) 3) spi reset only with applied v bb voltage stand-by current ? ? ? ? ?? 4) 4) when inx = low ? ? 5) 5) when dcr.mux = 111 b , inx = low and pcr.pst = 0 b ? idle current ????? ? ? ? 6) 6) when all channels are in off-state and dcr.mux 111 b ? diagnosis ? ? ? ? ? ? ? ?? 7) 7) current sense disabled in limp home mode
data sheet 14 rev. 1.0, 2010-04-12 spoc - BTS6460SF power supply activating one of the outputs via the input pi ns (inx = high) will wake-up the de vice out of stand-by mode. the power stages are working without vd d supply according to the table abov e. the output turn-on times will be extended by the stand-by channel wake up time t wu(stch) as long as no other channel is active. if one channel is active already before channel turn-on times t on ( 6.5.12 ) can be considered. note: in the operation with v dd = 0 v and inx = high a switching off of a ll input signals will turn the device in stand- by mode. in stand-by mode the error latches are cleared. limp home (lhi = high) applied for a time longer than t lh(ac) will wake-up the device out of stand-by mode after the power-on wake up time t wu(po) and it is working without vdd supply. channels 1, 2 and 3 can be activated via the input pins inx. the error latches can be cleared by a low-high tr ansition at the according input pin. 5.2 reset there are several reset trigger implemented in the de vice. they reset the spi registers including the over temperature latches to their default values. the po wer stages will switch off, if they are activated via the spi register out.n . if the power stages are activated via the parallel input pins they are not affected by the reset signals. the err-flags are cleared by those reset triggers. the over temperature protection and latches are functional after a reset trigger. note: during a reset only the channels 1, 2 and 3 can be activated via the according input pins. the input assigned mode is not available during a reset. the first spi transmission after any ki nd of reset contains at pin so the read information from the standard diagnosis, the transmission error bit ter is set. power-on reset the power-on reset is released, when v dd voltage level is higher than v dd(po) . the spi interface can be accessed after wake up time t wu(po) . reset command there is a reset command available to reset all register bi ts of the register bank an d the diagnosis registers. as soon as hwcr.rst = 1 b , a reset is triggered equivalent to power-on reset. the spi interface can be accessed after transfer delay time t cs(td) . limp home mode the limp home mode will be activate d as soon as the pin lhi is set to high for a time longer than t lh(ac) . the spi write-registers are reset with applied v bb voltage. the outputs outx can be acti vated via the input pins also during activated limp home mode. the error latches can be cleare d by a low-high transition at the according input pin. for application example see figure 30 . the spi interface is operating normally, so the limp home register bit lhi as well as the error flags can be read, but any write command will be ignored.
spoc - BTS6460SF power supply data sheet 15 rev. 1.0, 2010-04-12 5.3 electrical characteristics note: characteristics show the deviat ion of parameter at the given supp ly voltage and junction temperature. electrical characteristics power supply unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. 5.3.1 supply voltage range for normal operation power switch v bb(nor) 8?17v? 5.3.2 extended supply volt age range for operation power switch v bb(ext) 4.5 ? 28 1) 1) not subject to production test, specified by design. v parameter deviations possible 5.3.3 stand-by current for whole device with loads i bb(stb) ? ? ? ? 4.5 28 a v dd = 0 v v lhi = 0 v 1) t j = 25 c 1) t j 85 c 5.3.4 idle current for whole device with loads, all channels off i bb(idle) ?7?ma v dd = 5 v dcr.mux = 110 5.3.5 logic supply voltage v dd 3.0 ? 5.5 v ? 5.3.6 logic supply current i dd ? ? 140 280 ? ? a v cs = v lhi = 0 v r is = 2.7 k ? v is = 0 v f sclk = 0 hz f sclk = 5 mhz 5.3.7 logic idle current i dd(idle) ?25? a v cs = v dd f sclk = 0 hz chip in standby 5.3.8 operating current for whole device active i gnd ? 1025ma f sclk = 0 hz lhi input characteristics 5.3.9 l-input level at lhi pin v lhi(l) 0?0.8v? 5.3.10 h-input level at lhi pin v lhi(h) 1.8 ? 5.5 v ? 5.3.11 l-input current through lhi pin i lhi(l) 31280 a 1) v lhi = 0.4 v 5.3.12 h-input current through lhi pin i lhi(h) 10 40 80 a v lhi = 5 v reset 5.3.13 power-on reset threshold voltage v dd(po) ??2.4v? 5.3.14 power-on wake up time t wu(po) ??200 s 1) 5.3.15 stand-by channel wake up time t wu(stch) ??200 s 1) 5.3.16 limp home acknowledgement time t lh(ac) 5?200 s 1)
data sheet 16 rev. 1.0, 2010-04-12 spoc - BTS6460SF power supply 5.4 command description hwcr hardware configuration register 1) 1) shaded cells not mentioned in this chapter. w/r 2) 2) w/r write/read, rb register bank, addr address rb 2) addr 2) 9876543210 read 1 0 0 1 0 0 clktrim clk 0 led3 led2 stb cl write 1 0 0 1 0 0 clktrim clk 0 led3 led2 rst cl field bits type description rst 1 w reset command 0 1) normal operation 1 execute reset command 1) bold letters indicate the default values. stb 1 r stand-by 0 device is awake 1 device is in stand-by mode
spoc - BTS6460SF power stages data sheet 17 rev. 1.0, 2010-04-12 6 power stages the high-side power stages are built by n-channel vert ical power mosfets (dmos) with charge pumps. there are four channels implemented in the device. channels can be switched on via an input pin (please refer to section 6.2 ) or via spi register out. 6.1 output on-state resistance the on-state resistance r ds(on) depends on the supply voltage v bb as well as on the junction temperature t j . figure 4 shows those dependencies. the behavior in reverse polarity mode is described in section 8.5 . figure 4 typical on-state resistance 6.2 input circuit the outputs of the spoc - BTS6460SF can be activated either via the spi register out.outn or via the dedicated input pins. there are two different ways to use the input pins, the direct drive mode and the assigned drive mode. the default setting is the direct drive mode. to ac tivate the assigned drive mode the register bit icr.incg needs to be set. additionally, there are two ways of us ing the input pins in combination with the out register by programming the icr.col parameter. ? icr.col = 0 b : a channel is switched on either by the according out register bit or the input pin. ? icr.col = 1 b : a channel is switched on by the according out register bit only, when the input pin is high. in this configuration, a pwm signal can be applied to the i nput pin and the channel is activated by the spi register out . v bb = 13.5 v 0 5 10 15 20 25 30 35 40 45 50 -50 0 50 100 150 t j [c] r ds(on) [m ? ] channel 0,1 (bulb) channel 2,3 (bulb) channel 2,3 (led) t j = 25 c 0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 v bb [v] r ds(on) [m ? ] channel 0, 1 (bulb) channel 2,3 (bulb) channel 2,3 (led)
data sheet 18 rev. 1.0, 2010-04-12 spoc - BTS6460SF power stages figure 5 shows the complete input switch matrix. figure 5 input switch matrix the current sink to ground ensures t hat the input signal is low in case of an open input pin. the zener diode protects the input circ uit against esd pulses. 6.2.1 input direct drive this mode is the default after the device?s wake up and reset. the input pins activate the channels during normal operation (with default setting of bit icr.incg ), stand-by mode and limp home mode. channel 0 can be activated only via the spi-bit out.out0 in direct drive mode. the inputs are linked directly to the channels according to: inputmatrix_pwm .emf in1 incg gate driver 2 gate driver 1 gate driver 0 gate driver 3 & or out2 out1 out0 out3 & or col in2 & or & or in3 or & pwm generator ch0 ch1 ch2 ch3 freq-values pst ch0 ch1 ch2 ch3 pwm signals off/ on channel 0 freq0 freq1 or & &
spoc - BTS6460SF power stages data sheet 19 rev. 1.0, 2010-04-12 6.2.2 input assigned drive to activate the assigned drive function the register bit icr.incg needs to be set. in this mode all output channels can be activated via the input pins. channel 2 and 3 ar e assigned to only one input pin. the following mapping is used: 6.3 power stage output the power stages are built to be us ed in high side configuration ( figure 6 ). figure 6 power stage output the power dmos switches with a dedicated slope, which is optimized in terms of emc emission. defined slew rates and edge shaping allow lowe st emc emissions during pwm op eration at low switching losses. table 1 direct drive mode input pin assigned channel , if icr.incg = 0 b in1 channel 1 in2 channel 2 in3 channel 3 table 2 assigned drive mode input pin assigned channel , if icr.incg = 1 b in1 channel 0 in2 channel 1 in3 channel 2, channel 3 output .emf out gnd v out vbb v ds v bb
data sheet 20 rev. 1.0, 2010-04-12 spoc - BTS6460SF power stages 6.3.1 bulb and led mode channel 2 and channel 3 can be configured in bulb and led mode via the spi registers hwcr.ledn . during led mode following parameters are changed for an optimize d functionality with led loads: on-state resistance r ds(on) , switching timings ( t delay(on) , t delay(off) , t on , t off ), slew rates d v /d t on and d v /d t off , current protections i l(trip) and current sense ratio k ilis . 6.3.2 switching resistive loads when switching resistive loads the following s witching times and slew rates can be considered. figure 7 switching a load (resistive) 6.3.3 switching inductive loads when switching off inductive loads wi th high-side switches, the voltage v out drops below ground potential, because the inductance intends to cont inue driving the current. to prevent the destruction of the device due to high voltages, there is a voltage clamp mechanism implem ented, which limits that nega tive output voltage to a certain level ( v ds(cl) ( 6.5.2 )). see figure 6 for details. the device provides smartclamp functionality. to increase the energy capability, the clamp voltage v ds(cl) increases with the junction temperature t j and load current i l . please refer also to section 8.6 . the maximum allowed load inductance is limited. 6.4 inverse current behavior during inverse currents ( v out > v bb ) the affected channel stays in on- or in off-state. fu rthermore, during applied inverse currents no err-flag is set. the functionality of unaffected channel s is not influenced by inverse currents applied to other channels (except effects due to junction temperature increase). influences on the diagnostic function of unaffected channels are possible only for the current sense ratio, please refer to ? k ilis(ic) ( 9.8.3 ). note: no protection mechanism like temperature protection or current protection is active during applied inverse currents. inverse currents cause power losses inside the dmos, which increase the overall device temperature, which could lead to a switch off of the unaffected channels due to over temperature. v out t switchon.emf t on t off t 90% of v bb 10% of v bb 70% of v bb dv / dt on 30% of v bb 70% dv / dt off 30% t delay(on ) t delay(off ) in / outx t on(rise) t off (f all)
spoc - BTS6460SF power stages data sheet 21 rev. 1.0, 2010-04-12 6.5 electrical characteristics electrical characteristics power stages unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. output characteristics 6.5.1 on-state resistance r ds(on) m ? channel 0, 1 ? ? 3.5 7 ? 9 i l = 7.5 a 1) t j = 25 c t j = 150 c channel 2, 3 ? ? ? ? 11 22 39 78 ? 28 ? 100 hwcr.ledn = 0 i l = 2.6 a 1) t j = 25 c t j = 150 c hwcr.ledn = 1 i l = 0.6 a 1) t j = 25 c t j = 150 c 6.5.2 output clamp v ds(cl) v channel 0, 1 32 40 ? ? 54 55 t j = 25 c i l = 20 ma 1) t j = 150 c i l = 6 a channel 2, 3 32 40 ? ? 54 55 t j = 25 c i l = 20 ma 1) t j = 150 c i l = 2 a 6.5.3 output leakage current per channel in stand-by i l(offstb) a out.outn = 0 dcr.mux = 111 channel 0, 1 ? ? ? ? ? ? 2 10 50 t j = 25 c 1) t j = 85 c 1) t j = 105 c channel 2, 3 ? ? ? ? ? ? 1 4 20 t j = 25 c 1) t j = 85 c 1) t j = 105 c 6.5.4 output leakage current per channel in idle mode i l(offidle) a out.outn = 0 dcr.mux 111 channel 0, 1 ? ? ? ? ? ? 60 80 530 1) t j = 85 c 1) t j = 105 c t j = 150 c channel 2, 3 ? ? ? ? ? ? 45 50 230 1) t j = 85 c 1) t j = 105 c t j = 150 c
data sheet 22 rev. 1.0, 2010-04-12 spoc - BTS6460SF power stages 6.5.5 inverse current capability per channel -i l(ic) a 1) no influences on switching functionality of unaffected channels, k ilis influence according ? k ilis(ic) ( 9.8.3 ) channel 0, 1 6 ? ? channel 2, 3 2 ? ? input characteristics 6.5.6 l-input level v in(l) 0?0.8v? 6.5.7 h-input level v in(h) 1.8 ? 5.5 v ? 6.5.8 l-input current i in(l) 31280 a 1) v in = 0.4 v 6.5.9 h-input current i in(h) 10 40 80 a v in = 5 v electrical characteristics power stages (cont?d) unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spoc - BTS6460SF power stages data sheet 23 rev. 1.0, 2010-04-12 timings 6.5.10 turn-on delay to 10% v bb t delay(on) s 1) v bb = 13.5 v channel 0, 1 ? 25 ? ? channel 2, 3 ? ? 20 12 ? ? hwcr.ledn = 0 hwcr.ledn = 1 6.5.11 turn-off delay to 90% v bb t delay(off) s 1) v bb = 13.5 v channel 0, 1 ? 75 ? ? channel 2, 3 ? ? 50 20 ? ? hwcr.ledn = 0 hwcr.ledn = 1 6.5.12 turn-on time to 90% v bb including turn-on delay t on s v bb = 13.5 v dcr.mux 111 channel 0, 1 ? ? 100 r l = 2.2 ? channel 2, 3 ? ? ? ? 100 50 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 6.5.13 turn-off time to 10% v bb including turn-off delay t off s v bb = 13.5 v channel 0, 1 ? ? 150 r l = 2.2 ? channel 2, 3 ? ? ? ? 110 50 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 6.5.14 turn-on rise time from 10% to 90% v bb t on(rise) s v bb = 13.5 v dcr.mux 111 channel 0, 1 ? ? 55 r l = 2.2 ? channel 2, 3 ? ? ? ? 55 11 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 6.5.15 turn-off fall time from 90% to 10% v bb t off(fall) s v bb = 13.5 v channel 0, 1 ? ? 55 r l = 2.2 ? channel 2, 3 ? ? ? ? 55 11 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? electrical characteristics power stages (cont?d) unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
data sheet 24 rev. 1.0, 2010-04-12 spoc - BTS6460SF power stages 6.5.16 turn-on/off matching | t on - t off | s v bb = 13.5 v channel 0, 1 ? ? 90 r l = 2.2 ? channel 2, 3 ? ? ? ? 70 50 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 6.5.17 turn-on slew rate 30% to 70% v bb d v / d t on v/ s v bb = 13.5 v channel 0, 1 0.2 0.7 2.0 r l = 2.2 ? channel 2, 3 0.2 0.6 0.9 2.5 2.5 6.0 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 6.5.18 turn-off slew rate 70% to 30% v bb -d v / d t off v/ s v bb = 13.5 v channel 0, 1 0.2 0.7 2.0 r l = 2.2 ? channel 2, 3 0.2 0.6 0.9 2.5 2.5 6.0 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 1) not subject to production test, specified by design. electrical characteristics power stages (cont?d) unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spoc - BTS6460SF power stages data sheet 25 rev. 1.0, 2010-04-12 6.6 command description out output configuration registers w/r rb addr 9876543210 r/w00000 0 0 0 0 0 0 out3 out2 out1 out0 field bits type description outn n = 3 to 0 nrw set output mode for channel n 0 channel n is switched off 1 channel n is switched on 1) 1) channel status depends on automatic pwm generator configuration. for more details, please refer to section 7 . hwcr hardware configuration register w/r rb addr 9876543210 r/w10010 0 clktrim clk 0 led3 led2 stb cl field bits type description ledn n = 3 to 2 nrw set led mode for channel n 0 channel n is in bulb mode 1 channel n is in led mode icr inputand current source configuration register w/r rb addr 9876543210 r/w10001 0 0 0 0 0 0colincg csl 0 field bits type description incg 2 rw input drive configuration 0 direct drive mode 1 assigned drive mode col 3 rw input combinatorial logic configuration 0 input signal or-combined with according out register bit 1 input signal and-combined with according out register bit
data sheet 26 rev. 1.0, 2010-04-12 spoc - BTS6460SF automatic pwm generator 7 automatic pwm generator the spoc - BTS6460SF has an automatic pwm generator implemented, which allows to operate the channels in pwm mode with drastically reduced mi cro controller attention compared to a conventional pwm generation via spi. after the initializing phase, wher e different settings are done, the pwm generator works autonomously. the only required information from the micro controller is the pwm duty cycle and the channel states (on-state or off-state). for details about the current sense diagnosis please refer to chapter 9 . 7.1 pwm setup the pwm operation mode is available for each output. the register chcrn.freq is used to switch from normal mode to automatic pwm generation mode. with chcrn.freq = 00 b the output state is following the outn register value. for details please refer to figure 5 . to start the automatic pwm generation the bit pcr.pst has to be set. for details please refer to figure 8 . the device can be woken up also out of stand-by mode by setting the bit pcr.pst . therefore, the power-on wake up time t wu(po) ( 5.3.14 ) has to be considered as delay until the automati c pwm generation will start. 7.2 pwm clock the output pwm frequency f pwm can be derived from an external clock f pclk , which is applied at the pin pclk, or from an internal clock f int . the source for the pwm clock can be select ed by the spi register hwcr.clk . note: for avoiding skews it is recommended to change from external to internal clock source or vice versa only during deactivated pwm generator ( pcr.pst = 0 b ). 7.2.1 external pwm clock the output pwm frequency is generated from the pwm clock input signal f pclk (applied at the pin pclk), if hwcr.clk is set to 0 b . the resulting output pwm frequency clock f pwm is: (1) the prescaler is set via the register chcrn.freq according to: for example: with f in =102,400 hz ? chcrn.freq = 01 b : f pwm = 400 hz ? chcrn.freq = 10 b : f pwm = 200 hz ? chcrn.freq = 11 b : f pwm = 100 hz note: for avoiding skews it is recommended to change the prescaler setting only during deactivated pwm generator ( pcr.pst = 0 b ). table 3 prescaler setting prescaler setting chcrn.freq resulting prescaler 00 b normal mode without automatic pwm generation 01 b prescaler 1: f pclk (or f int ) / 256 10 b prescaler 2: f pclk (or f int ) / 512 11 b prescaler 4: f pclk (or f int ) / 1024 f pwm f pclk 256 prescaler ? -------------------------------------- =
spoc - BTS6460SF automatic pwm generator data sheet 27 rev. 1.0, 2010-04-12 the applied clock signal can be monitored via spi in the standard diagnosis. t he standard diagnosis bit cle provides the information in device operat ion mode (not during stand-by), if th e applied clock is above or below the threshold f pclk(th) according to the following table. the bit cle will be reset after every successful standard diagnosis readout. the reset of the bit cle is performed only, if the bit cle is set. note: a changing of the hwcr.clktrim will also change the cle thresholds. 7.2.2 internal pwm clock the spoc - BTS6460SF provides also an internal clock signal f int . the internal clock frequency is used by setting the register hwcr.clk to 1 b . for adjusting the clock signal, a trimming of f int via the spi register hwcr.clk_trim can be done. f pwm can be decreased or increased in steps of k trim . (2) 7.3 pwm duty cycle the pwm duty cycle of each output is defined by the spi register dccrn.dc register from 0 to 256. the on-state duty cycle is (in %): (3) the minimum duty cycle, which can be se t (except from 0 %), is according to equation (3) 0.39 %. the duty cycle of the output voltage depends on the switching times t on , t off an d the connected load. th erefore, the observed output duty cycle can differ from the set duty cycle. 7.4 channel phase shift for optimized emc performances phase shifts betwe en all channels can be programmed via the spi register chcrn.phs . the phase shifts refer to one common start point. please refer to figure 8 . up to eight different phase shifts can be selected. table 4 external clock monitoring external clock status cle clock frequency 0 b f pclk > f pclk(th) 1 b f pclk < f pclk(th) f pwm f int x k trim ? () 256 prescaler ? -------------------------------------- = dc pwm dccrn.dc 100 ? 256 ------------------------------------------------- - =
data sheet 28 rev. 1.0, 2010-04-12 spoc - BTS6460SF automatic pwm generator figure 8 phase shifts between channels 7.5 daisy chain operation with pwm generator the spi of spoc - BTS6460SF provides daisy chain capability. in this configuration se veral devices are activated by the same cs signal mcs . this allows the usage of only one pwm clock input signal f pclk . to avoid a synchronous activation of channels of the different devices, device phase shift can be programmed at the register pcr.dpsh . 7.5.1 activation of s everal spoc devices with pwm generation for the usage of several spoc devices in daisy chain configuration with automatic pwm generation the following procedure is recommended: ? wake up the devices by setting the dcr.mux 111 b ? set the pwm frequencies, duty cycles , phase shifts of all channels ? set the device phase shift for each spoc device differently ? activate the automatic pwm generator of all devices by setting pcr.pst within one mcs -frame ? activate the channels via the spi registers out.outn with the next rising edge of the pwm clock signal f pwm the automatic pwm generation will start. please see figure 9 for details. note: if the pwm generator is started during stand-by, the powe r-on wake up time t wu(po) ( 5.3.14 ) has to be considered as delay until the au tomatic pwm generation will start. channelphaseshift .emf t v pclk t pcr.pst t v out0 t out.out0 t v out1 t out.out1 t pclk dc pwm0 t pwm0 t ch. phase shif t 1
spoc - BTS6460SF automatic pwm generator data sheet 29 rev. 1.0, 2010-04-12 figure 9 phase shifts between devices 7.5.2 how to resynchronize a reset spoc in case of a reset spoc device or a spoc device in st and-by mode the synchronization can be done as follows: ? set the pwm frequencies, duty cycles, phase shifts of the reset device ? set the device phase shift for the reset spoc device ? deactivate the automatic pwm generation of all spoc devices in this daisy chain ? with the next spi transmission activate the automatic pwm generator of all spoc devices by setting pcr.pst within one mcs -frame ? activate the channels of the reset spoc device via the spi register out.outn with the next rising edge of the pwm clock signal f pwm the automatic pwm generation will start again synchronously. t v pclk t pcr.pst t v out0 t out.out0 t out.out0 devicephaseshift.emf t v out0 t dev. phase shif t 1 t pcr.pst dc pwm0 t t v out1 t dev. phase shif t 1 t ch. phase shif t 1 dc pwm1 device 1 device 2 out.out1
data sheet 30 rev. 1.0, 2010-04-12 spoc - BTS6460SF automatic pwm generator 7.6 electrical characteristics electrical characteristics power stages unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. 7.6.1 external pwm clock threshold f pclk(th) 22 ? 46 khz hwcr.clktrim = 100 7.6.2 external pwm clock f pclk ??250khz ? 7.6.3 external pwm clock period t pclk(p) 4?? s 1) 1) not subject to production test, specified by design. functional test is performed at f pclk = 250khz. 7.6.4 external pwm clock high time t pclk(h) 2?? s 1) 7.6.5 external pwm clock low time t pclk(l) 2?? s 1) 7.6.6 external pwm clock duty cycle range dc pclk 30 % ?70 % 1) 7.6.7 internal pwm clock f int 75 105 135 khz hwcr.clktrim = 100 7.6.8 internal pwm clock trimming step k trim ?5 % ? 2) 2) not subject to production test, specified by design.
spoc - BTS6460SF automatic pwm generator data sheet 31 rev. 1.0, 2010-04-12 7.7 command description hwcr hardware configuration register w/r rb addr 9876543210 read 1 0 0 1 0 0 clktrim clk 0 led3 led2 stb cl write 1 0 0 1 0 0 clktrim clk 0 led3 led2 rst cl field bits type description clk 5 rw clock mode 1) 0 external clock input pclk is used for pwm mode 1 internal clock is used for pwm mode 1) for avoiding skews it is recommended to change from external to internal clock source or vice versa only during deactivated pwm generator ( pcr.pst = 0 b ). clktrim 8:6 rw internal clock trim 000 f int - 4 k trim ... 011 f int - 1 k trim 100 f int without trimming 101 f int + 1 k trim ... 111 f int + 3 k trim standard diagnosis cs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ter 0 lhi sbm xcle x x x x x x x err3 err2 err1 err0 field bits type description cle 11 r external clock status 1) 0 f pclk > f pclk(th) 1 f pclk < f pclk(th) 1) invalid in stand-by mode
data sheet 32 rev. 1.0, 2010-04-12 spoc - BTS6460SF automatic pwm generator chcrn channel configuration register w/r rb addr 9876543210 r/w110xx 0 0 0 phsn sydeln freqn field bits type description freqn n = 0 to 3 1:0 rw pwm frequency prescaler setting for channel n 00 normal mode without automatic pwm generation 01 prescaler 1: f pclk (or f int ) / 256 10 prescaler 2: f pclk (or f int ) / 512 11 prescaler 4: f pclk (or f int ) / 1024 sydeln n = 0 to 3 3:2 rw delay of current sense synchronization signal for channel n 00 no synchronization signal delay 01 synchronization signal delay 1: 8 / ( f pclk (or f int )) 10 synchronization signal delay 2: 16 / ( f pclk (or f int )) 11 synchronization signal delay 3: 24 / ( f pclk (or f int )) pshn n = 0 to 3 6:4 rw channel phase shift for channel n 000 no phase shift 001 phase shift 1: 32 / ( f pclk (or f int )) 010 phase shift 2: 64 / ( f pclk (or f int )) ... 110 phase shift 6: 192 / ( f pclk (or f int )) 111 phase shift 7: 224 / ( f pclk (or f int )) pcr pwm configuration register w/r rb addr 9876543210 r/w00111 0 0 0 0 0 0 dcs dpsh pst field bits type description pst 0 rw automatic pwm generation 0 no automatic pwm generation 1 automatic pwm generation dpsh 2:1 rw device phase shift 00 no phase shift 01 phase shift 1: 8 / ( f pclk (or f int )) 10 phase shift 2: 16 / ( f pclk (or f int )) 11 phase shift 3: 24 / ( f pclk (or f int )) dcs 3 rw single duty cycle for all channels 0 duty cycle setting of channel 0 used for all channels 1 individual duty cycle settin g used for each channel
spoc - BTS6460SF automatic pwm generator data sheet 33 rev. 1.0, 2010-04-12 dccrn duty cycle configuration register w/r rb addr 9876543210 r/w010xx 0 dcn field bits type description dcn n = 0 to 3 8:0 rw duty cycle for channel n during automatic pwm generation 000000000 dc value: 0 (channel off) 000000001 dc value: (1 / 256) * 100 000000010 dc value: (2 / 256) * 100 ... 011111111 dc value: (255 / 256) * 100 1xxxxxxxx dc value: 1 (channel 100% on)
data sheet 34 rev. 1.0, 2010-04-12 spoc - BTS6460SF protection functions 8 protection functions the device provides embedded protective functions, wh ich are designed to prevent ic destruction under fault conditions described in this data sheet. fault condit ions are considered as ?out side? normal operating range. protective functions are neither designed fo r continuous nor for repetitive operation. 8.1 over current protection the maximum load current i l is switched off in case of exceeding the over current trip level i l(trip) by the device itself. depending on the total short circuit impedance high er current over shoots may occur. a limited auto-restart function is implemented. the number of restarts is dependent of the v ds voltage. please refer to following figures for details. figure 10 over current protection with latch due to reaching maximum number of retries n retry i l i is t t t err t currenttr ippingdeltat_nretry.emf cl = 1 v ds t v ds(vt rip) i l(t rip) over current normal operation in / outx t t j t j(st art n) + ? t j(res) t j(st art 1) t j(st art 1) + ? t j(res) t j(st art 2) + ? t j(res) n = 1 over load removed t j(sc) n= n retry * err-flag will be r eset by standard diagnosis r eadout during restart * switch off by over curr ent switch off restart by dynamic temperature sensor latch off due maxi mum number of retries reached
spoc - BTS6460SF protection functions data sheet 35 rev. 1.0, 2010-04-12 figure 11 over current protection with latch due to reaching over temperature t j(sc) the err-flag will be set during over cu rrent shut down. it can be reset by reading the err-flag . if the channel is still in over current shut down, the err-flag will be set ag ain. during the automatic re start of the ch annel the err- flag can be cleared by reading the err-fl ag. it will be set again as soon as th e over current protection is activated again. the number of restarts n retry is depending on the v ds voltage according to the following figure and chapter 8.2 . figure 12 number of retries and trip levels dependent of v ds the retry latch or over temperature latch is cleared by spi command hwcr.cl = 1 b . if the input pin or the bit in the spi register out is still set, the channel will be turned on i mmediately (or according to the automatic pwm generator setting) after the command hwcr.cl = 1 b . i l i is t t t err t currenttrippingdeltat_ot.emf cl = 1 v ds t v ds(vt rip) i l(t rip) over current normal operation in / outx t t j t j(st art n) + ? t j(res) t j(st art 1) t j(st art 1) + ? t j(res) t j(st art 2) + ? t j(res) n = 1 over load removed t j(sc) n < n retry * err-flag will be r eset by standard diagnosis r eadout during restart * switch off by over curr ent switch off restart by dynamic temperature sensor latch off due to over temperature i l i l(t rip) v ds 5 10 15 20 i l(vt rip) n= n retry(lv) n= n retry(mv) no retry currenttrippingvsvds.emf
data sheet 36 rev. 1.0, 2010-04-12 spoc - BTS6460SF protection functions 8.2 over current pr otection at high v ds the spoc - BTS6460SF provides an over current protection for v ds > v ds(vtrip) ( 8.9.5 ). for v ds > v ds(vtrip) and i l > i l(vtrip) during turn on the channel switches off and latche s immediately. for details please refer to parameter i l(vtrip) ( 8.9.4 ). the current trip level i l(vtrip) is below the current trip level i l(trip) at v ds = 7v. the ratio between i l(trip) and i l(vtrip) is defined by the parameter ? k tr ( 8.9.6 ). the over current latch is cleared by spi command hwcr.cl = 1 b . if the input pin or the bit in the spi register out is still set, the channel will be turn ed on immediately (or according to th e automatic pwm gen erator setting) after the command hwcr.cl = 1 b . figure 13 over current protection in case of high v ds voltages 8.3 over current protection for s hort circuit type 2 protection after activation of the channels without over temperature shutdown and after the delay time t delay(trip) ( 8.9.2 ) the over current protection threshold i l(trip) is reduced to i l(itrip) . the delay time t delay(trip) is reset by an dynamic temperature sensor or over current shutdown and any in, outx or automatic pwm generator signal transition. in case of a short circuit to gnd event with i l > i l(itrip) ( 8.9.3 ), which occurs in the on st ate, the channel is switched off and latched immediately. for more details, please refer to the figure figure 14 . the current trip level i l(itrip) is below the current trip level i l(trip) at v ds = 7v. the ratio between i l(trip) and i l(itrip) is defined by the parameter ? k tr ( 8.9.6 ). the over current latch is cleared by spi command hwcr.cl = 1 b . if the input pin or the bit in the spi register out is still set, the channel will be turn ed on immediately (or according to th e automatic pwm gen erator setting) after the command hwcr.cl = 1 b . i l i is t t t err t currenttrippinghighvds.emf cl = 1 v ds t v ds(vt rip) i l(vt rip) high v ds over current normal operation over load removed in / outx
spoc - BTS6460SF protection functions data sheet 37 rev. 1.0, 2010-04-12 figure 14 shut down by over current due to short circuit type 2 8.4 over temperature protection each channel has its own temperature sensor. if the te mperature at the channel exceeds the thermal shutdown temperature t j(sc) , the channel will switch off and latch to prevent destruction (also in case of v dd = 0v). in order to reactivate the channel, the temperature at the ou tput must drop by at leas t the thermal hysteresis ? t j and the over temperature latch must be cleared by spi command hwcr.cl = 1 b . if the input pin or the bit in the spi register out is still set, the channel will be turned on immedi ately (or according to th e automatic pwm generator setting) after the command hwcr.cl = 1 b . figure 15 shut down by over temperature 8.4.1 dynamic temperature sensor protection additionally, each channel has its own dynamic temperat ure sensor. the dynamic temperature sensor improves short circuit robustness by limiting sudden increases in the junction temperature. th e dynamic temperature sensor turns off the channel if its sudden temperature incr ease exceeds the dynamic tem perature sensor threshold ? t j(sw) . the number of automatic re activations is limited by n retry ( 8.9.7 ). if this number of retries is exceeded the channel turns off and latches. the re try latch is cleared by spi command hwcr.cl = 1 b . if the input pin or the bit in the spi register out is still set, the channel will be turned on im mediately (or according to the automatic pwm generator setting) after the command hwcr.cl = 1 b . for the condition n < n retry the counter of automatic reactivations will be reset by every low to high transition on the inpu t pin or the bit in spi register out . i l i is t t t err t current t rippinglowvds . emf cl = 1 i l ( itr ip ) normal operation over current normal operation over load remov ed in / outx t > t delay(trip) i l i is t t t err t overload .emf cl = 1 in / outx cl = 1 i l(t rip) t t j t j(st art 1) t j(st art 1) + ? t j(sw ) t j(sc) latch off due to over temperature latch off due to over temperature
data sheet 38 rev. 1.0, 2010-04-12 spoc - BTS6460SF protection functions for automatic pwm generation the coun ter will be reset also in case of du ty cycles < 100% during the off-state. please refer to figure 14 for details. figure 16 dynamic temperature sensor operations with latch due to reaching maximum number of retries n retry i is t t err t deltat_nretry.emf cl = 1 over load normal operation in / outx t t j n = 1 over load removed t j(sc) n= n retry * err-flag will be reset by st andard diagnosis readout during restart * latch off due maximum number of r etries reached i l t v ds t v ds(vt rip) i l(t rip) t j(st art 1) + ? t j(res) t j(st art 1) + ? t j(sw ) switch off by dynamic temperature sensor restart by dynamic temperature sensor ? t jsw t j(st art n) + ? t j(res) t j(st art 1)
spoc - BTS6460SF protection functions data sheet 39 rev. 1.0, 2010-04-12 figure 17 dynamic temperature sensor operations with latch due to reaching over temperature t j(sc) the err-flag will be set during dynamic temperature sensor shut down. it can be reset by read ing the err-flag. if the channel is still in dynamic temperature sensor shut down, the err-flag will be set again. during the automatic restart of the channel the e rr-flag can be cleared by reading t he err-flag. it will be set again as soon as the dynamic temperature sensor is activated again. 8.5 reverse polarity protection in reverse polarity mode, power dissipation is caused by the intrinsic body diode of each dmos channel as well as each esd diode of the logic pins. the reverse current through the channels has to be limited by the connected loads.the current through the ground pin, sense pin is, cu rrent sense synchronization pin, the logic power supply pin vdd, the spi pins, input pins, cloc k input pin and the limp home input pin has to be limited as well (please refer to the maximum ratings listed on page 10 ). for reducing the power loss during reverse polarity reversave tm functionality is implemented for all channels. they are turned on to almost forward condition in reverse polarity condition, see parameter r ds(rev) . note: no protection mechanism like temper ature protection or current protection is active during reverse polarity. 8.6 over voltage protection in the case of supply voltages between v bb(sc) max and v bb(cl) the output transistors ar e still operational and follow the input or the out register. parameters are not warranted and lif etime is reduced compared to normal mode. in addition to the output clamp for inductive loads as described in section 6.3 , there is a clamp mechanism available for over voltage protecti on for the logic and all channels. i l i is t t t err t deltat_ot.emf cl = 1 v ds t v ds(vt rip) i l(t rip) over load normal operation in / outx t t j t j(st art n) + ? t j(res) t j(st art 1) t j(st art 1) + ? t j(res) t j(st art 1) + ? t j(sw ) n = 1 over load removed t j(sc) n < n retry * err-flag will be reset by st andard diagnosis readout during restart * switch off by dynamic temperature sensor restart by dynamic temperature sensor latch off due to over temperature ? t jsw
data sheet 40 rev. 1.0, 2010-04-12 spoc - BTS6460SF protection functions 8.7 loss of ground in case of complete loss of the device ground co nnections, but connected load ground, the spoc - BTS6460SF securely changes to or stays in off-state. 8.8 loss of v bb in case of loss of v bb connection in on-state, all inductances of the loads have to be demagnetized through the ground connection or th rough an additional path from vbb to gr ound. for exam ple, a suppre ssor diode is recommended between vbb and gnd.
spoc - BTS6460SF protection functions data sheet 41 rev. 1.0, 2010-04-12 8.9 electrical characteristics electrical characteri stics protection functions unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. over load protection 8.9.1 load current trip level i l(trip) a v ds < 7 v channel 0, 1 71 ? 67 ? 90 ? 120 ? 100 t j = -40 c 1) t j = 25 c t j = 150 c channel 2, 3 29 ? 23 ? 30 ? 44 ? 39 hwcr.ledn = 0 t j = -40 c 1) t j = 25 c t j = 150 c 7 ? 5.5 ? 8.5 ? 12 ? 11 hwcr.ledn = 1 t j = -40 c 1) t j = 25 c t j = 150 c over current protection 8.9.2 over current tripping activation time t delay(trip) 7?14ms 1) 8.9.3 load current trip level after t delay(trip) i l(itrip) a channel 0, 1 40 35 ? ? 78 70 t j = -40 c t j = 150 c channel 2, 3 17 15.5 ? ? 35 30 hwcr.ledn = 0 t j = -40 c t j = 150 c 3.8 3.8 ? ? 9 8 hwcr.ledn = 1 t j = -40 c t j = 150 c 8.9.4 load current trip level at high v ds i l(vtrip) a 1) channel 0, 1 40 35 ? ? 78 70 t j = -40 c t j = 150 c channel 2, 3 17 15.5 ? ? 35 30 hwcr.ledn = 0 t j = -40 c t j = 150 c 3.8 3.8 ? ? 9 8 hwcr.ledn = 1 t j = -40 c t j = 150 c 8.9.5 over current tripping at high v ds activation level v ds(vtrip) 15??v 1) 8.9.6 current trip at v ds = 7 v to current trip at v ds = 20 v ratio ? k tr 1.2 1.5 ? 1)
data sheet 42 rev. 1.0, 2010-04-12 spoc - BTS6460SF protection functions over temperature protection 8.9.7 number of automatic retries at over current or dynamic temperature sensor shut down at low v ds n retry(lv) ?32? 1) v ds = 9 v 8.9.8 number of automatic retries at over current or dynamic temperature sensor shut down at medium v ds n retry(mv) ?8? 1) v ds = 13 v 8.9.9 thermal shut down temperature t j(sc) 150 175 195 c 1) 8.9.10 thermal hysteresis of thermal shutdown ? t j ?10?k 1) 8.9.11 dynamic temperature increase limitation while switching ? t j(sw) ?60?k 1) 8.9.12 dynamic temperature sensor restart ? t j(res) ?20?k 1) reverse battery 8.9.13 on-state resistance r ds(rev) m ? 1) v bb = -13.5 v channel 0, 1 ? ? 4.7 9.5 ? ? i l = -7.5 a t j = 25 c t j = 150 c channel 2, 3 ? ? 14.7 29.5 ? ? i l = -2.6 a t j = 25 c t j = 150 c over voltage 8.9.14 over voltage protection v bb(cl) v vbb to gnd 40 55 70 i gnd = 5 ma channel 0, 1 32 40 ? ? 54 55 t j = 25 c i l = 20 ma 1) t j = 150 c i l = 6 a channel 2, 3 32 40 ? ? 54 55 t j = 25 c i l = 20 ma 1) t j = 150 c i l = 2 a 1) not subject to production test, specified by design. electrical characterist ics protection functions (cont?d) unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spoc - BTS6460SF protection functions data sheet 43 rev. 1.0, 2010-04-12 8.10 command description hwcr hardware configuration register w/r rb addr 9876543210 read 1 0 0 1 0 0 clktrim clk 0 led3 led2 stb cl write 1 0 0 1 0 0 clktrim clk 0 led3 led2 rst cl field bits type description cl 0 rw clear latch 0 thermal and over current latches are untouched 1 command: clear all thermal and over current latches standard diagnosis cs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ter 0 lhi sbm x cle x x x x x x x err3 err2 err1 err0 field bits type description errn n = 0 to 3 3:0 r error flag for channel n 0 no error 1 error occurred
data sheet 44 rev. 1.0, 2010-04-12 spoc - BTS6460SF diagnosis 9 diagnosis for diagnosis purpose, the spoc - BTS6460SF provides a cu rrent sense signal at pin is and the diagnosis word via spi. there is a current sense multiplexer implemented that is controlled via spi. the sense signal can also be disabled by spi command. a switch bypass monitor allows to detect a short circuit between the output pin and the battery voltage. in off-state a current source is able to be switched on for a selected channel with the dcr.csol bit. this allows open load / short circuit detection to v bb in off-state. the current value can be configured to a low or a high value by programming the bit iecr.csl . please refer to parameter i l(ol) ( 9.8.15 ). please refer to figure 18 for details on diagnosis function: figure 18 block diagram: diagnosis channel 0 load current sense diagnosis_std .emf r is i is0 current sense multiplexer is t gate control latch temperature sensor err0 or latch dcr.mux v bb v ds(sb) sbm dcr. out3 out2 out1 out0 vbb csol over current protection i l(ol)
spoc - BTS6460SF diagnosis data sheet 45 rev. 1.0, 2010-04-12 for diagnosis feedback at different oper ation modes, please see following table. 9.1 diagnosis word at spi the standard diagnosis at the spi in terface provides information about each channel. the error flags, an or combination of the over temperature flags and the over lo ad monitoring signals are provided in the spi standard diagnosis bits errn . the over load monitoring signals are latched in the erro r flags and cleared each time the standard diagnosis is transmitted via spi. in detail, they are cleared between the second and third raising edge of the sclk signal. the over temperature flags, which cause an overheated channel to latch off, are latched directly at the gate control block. the over current flags, which cause an channel 0 or 1 driving a too high current to switch off, are latched like the over temperature flags. those latches are cleared by spi command hwcr.cl . please note: the over temperature and over current informat ion is latched twice. when transmitting a clear latch command ( hwcr.cl ), the error flag is cleared during command tr ansmission of the next spi frame and ready for latching after the third raising edge of the sclk signal. as a result, the first standard diagnosis information after a cl command will indicate a failure mode at the previously affected chann els although the th ermal latches have been cleared already. in case of continuous over load, t he error flags are set again immediately because of the over load monitoring signal. 9.2 load current sense diagnosis there is a current sense signal available at pin is which provides a current proportional to the load current of one selected channel. the selection is done by a multiplexer which is configured via spi. table 5 operation modes 1) 1) l = low level, h = high level, z = high impedance, potential d epends on leakage currents and external circuit x = undefined operation mode input level out.outn output level v out current sense i is error flag errn 2) 2) the error flags are latched until they are tr ansmitted in the standard diagnosis word via spi sbm dcr.sbm normal operation (off) l / 0 (off-state) gnd z 0 1 short circuit to gnd gnd z 0 1 thermal shut down z z 0 x short circuit to v bb v bb z 0 0 open load z z 0 0 3) 3) if the current sense multiplexer is set to channel 0 to 3 and drc.csol bit set inverse current > v bb z 0 0 4) 4) if the current sense multiplexer is set to channel 0 to 3 normal operation (on) h / 1 (on-state) ~ v bb i l / k ilis 00 short circuit to gnd ~ gnd z 1 1 dynamic temperature sensor shut down z z 1 x over current shut down z z 1 5) 5) the over current latch off flag is set la tched and can be cleared by spi command hwcr.cl x thermal shut down z z 1 6) 6) the over temperature flag is set latc hed and can be cleared by spi command hwcr.cl x short circuit to v bb v bb < i l / k ilis 00 open load v bb z00 inverse current > v bb z00
data sheet 46 rev. 1.0, 2010-04-12 spoc - BTS6460SF diagnosis current sense signal the current sense signal (ratio k ilis = i l / i s ) is provided during on-state as long as no failure mode occurs.the ratio k ilis can be adjusted to the load type (led or bulb) via spi register hwcr for channel 2 and 3. the accuracy of the ratio k ilis depends on the load current.usually a resistor r is is connected to the current sense pin. it is recommended to use resistors 1.5 k ?< r is <5k ? . a typical value is 2.7 k ? . figure 19 current sense ratio k ilis channel 0, 1 1) figure 20 current sense ratio k ilis channel 2, 3 2) in case of off-state, over current, dy namic temperature sensor shut down ( n < n retry ), dynamic temperature sensor latch ( n = n retry ) as well as over temperature, the current sense signal of the affected channel is switched off. to distinguish between over temperature or over curren t and over load, the spi diagnosis word can be used. whereas the over load and dynamic temperature sensor shut down ( n < n retry ) flag is cleared every time the diagnosis is transmitted. the over temperat ure, dynamic temperature sensor latch ( n = n retry ) and over current flag is cleared by a dedicated spi command ( hwcr.cl ). 1) the curves show the behavior based on characterization dat a. the marked points are guaranteed in this data sheet in section 9.8 (position 9.8.1 ). 2) the curves show the behavior based on characterization dat a. the marked points are guaranteed in this data sheet in section 9.8 (position 9.8.1 ). 0 10000 20000 30000 40000 50000 60000 012345678 load current i l [a] k ilis value kilis tj = -40 c kilis typ tj = 25 c kilis tj = 25 c, 150 c 0 500 1000 1500 2000 2500 3000 3500 4000 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 load current i l [a] k ilis value kilis bulb tj = 25 c, 150 c kilis bulb typ tj = 25 c kilis bulb tj = -40 c kilis led tj = 25 c, 150 c kilis led typ tj = 25 c kilis led tj = -40 c
spoc - BTS6460SF diagnosis data sheet 47 rev. 1.0, 2010-04-12 details about timings between the current sense signal i is and the output voltage v out and the load current i l can be found in figure 21 . figure 21 timing of current sense signal current sense multiplexer there is a current sense multiplexer implemented in the spoc - BTS6460SF that routes the sense current of the selected channel to the diagnosis pin is. the channel is selected via spi register dcr.mux . the sense current also can be disabled by spi register dcr.mux . for details on timing of the current sense multiplexer, please refer to figure 22 . figure 22 timing of current sense multiplexer senset iming . emf v out i is t t t i l t on t on t sis( o n) t sis( l c) off t off t dis(off) off outx muxt iming . emf cs i is t t 000 dcr.mux 010 110 110 t sis( en) t sis( mux) t d is( mux)
data sheet 48 rev. 1.0, 2010-04-12 spoc - BTS6460SF diagnosis 9.3 sense synchronization duri ng automatic pwm generation for performing current sens e measurements there is a current sense synchronization signal at the pin issy available. this signal indicates the possible start of v is measurement. the synchronizat ion signal will be activated after the time t measurement delay after channel?s activation. the delay time can be configured via spi register chcrn.sydel . the current sense syn chronization signal is only availabl e during the automatic pwm generation, i.e. the bit pcr.pst is set. figure 23 shows the functionality of the cu rrent sense synchronization signal. figure 23 current sense synchronization sensesynchronization .emf t v pclk t pcr.pst t v out0 t out.out0 t v out1 t t v issy t synch. delay1 t v is t dcr.mux 001 001 000 001 t synch. delay0 t sis(on) out.out1 t ch. phase shif t 1
spoc - BTS6460SF diagnosis data sheet 49 rev. 1.0, 2010-04-12 9.4 sense measurement without synchronization signal the spoc - BTS6460SF refers all the channel activations to the clock signal f pclk or f int . in case of using the external clock f pclk the state (on- or off-state) is known by the micro controller, which allows a time based processing. in case of micro controller?s loss of the pclk synchron y the automatic pwm generation can be started again by resetting and setting of the bit pcr.pst . after that the micro controller is synchronous to the automatic pwm generation. 9.5 automatic current sen se multiplexer switching the device provides for current sense measurements a function, which changes the current sense multiplexer sequentially and automatically. the function starts af ter the pwm reference point has passed, which happens each 1024 clock cycles ( f pclk or f int ). for more details please refer to figure figure 23 . the current sense multiplexer is switched first to the channel 0. when the current sense syn chronization signal at the pin issy is finished, the multiplexer is programmed automatically to channel 1 (one clock cycle after the high low transition of the issy signal) and so on. th e current sense syn chronization signal at the pin issy will be set for eight clock cycles, if the channel duty cycle is 0 % < dc <100 %. for the scenario, where th e channel is continuously on ( dc = 100 %) or off ( dc = 0 %), or the t issy delay > t duty cycle (delay longer than on-state of channel) the sense synchronization signal will be set for nine clock cycles ( f pclk or f int ). furthermore, to shor ten the issy burst length for channels continuously in on- or off-state, the issy signal will be started 11 clock cycle s after the previous issy pulse. if the synchronization delay is programmed to 11 b the following channel needs at minimum a synchronization delay = 01 b , otherwise the ne xt issy signal will be delayed by on e period of the following channel. this multiplexer switch ing loop is done only once after the bit dcr.amux is set. after the completed loop the bit will be set to dcr.amux = 0 b automatically. for more details please refer to figure 23 . the automatic multiplexer switching can be stopped manually by setting the bit dcr.amux = 0 b . note: the phase shifts between the channels have to be programmed in ascending order (channel 0 with minimum phase shift, channel 1 with a higher phase shift than channel 0, channel 2 with a higher phase shift than channel 1, ...) to get a short amux burst durati on. otherwise the duration for a complete automatic multiplexer cycle will increa se until a new pwm reference point has passed and the channel is activated. during the activated amux bit any command, which should change the multiplexer, will be ignored. if a channel is switched continuously off, the current se nse multiplexer will be switch ed to high impedance during the sense synchronization pulse.
data sheet 50 rev. 1.0, 2010-04-12 spoc - BTS6460SF diagnosis figure 24 automatic current sense multiplexer switching 9.6 switch bypass diagnosis to detect short circuit to v bb , there is a switch bypass monitor implemente d. in case of short circuit between the output pin out and v bb in on-state, the curr ent will flow through the power transistor as we ll as through the short circuit (bypass) with undefined ratio. as a result, the current sense signal will show lower values than expected by the load current. in o ff-state, the outp ut voltage will stay close to v bb potential which means a small v ds . the switch bypass monitor compares the voltage v ds across the power transistor of that channel, which is selected by the current sense multiplexer ( dcr.mux ) with threshold v ds(sb) . the result of comparison can be read in spi register dcr.sbm or in the standard diagnosis. automux .emf t v pclk t pcr.pst t dcr.amux t v issy t v out2 t ch. phase shif t 2 t synch. delay0 t synch. high a * t v out3 t ch. phase shif t 3 t v is t sis(on) t i ssy delay o n/ o f f t synch. delay2 t synch. high b * t synch. high a * t synch. high b * ch0 ch1 ch2 ch3 n * 1024 set to 0 automati cal l y t v out0 t v out1 t ch. phase shift1 t issy delay on/off * t synch. high a = 8 / ( f pclk or f int ) * t issy delay on/off = 11 / ( f pclk or f int ) * t synch. high b = 9 / ( f pclk or f int )
spoc - BTS6460SF diagnosis data sheet 51 rev. 1.0, 2010-04-12 9.7 open load in off-state for performing a dedicated open load in off-state dete ction a current source can be switched in parallel to the dmos accord ing to the figure 18 . the current source current can be programmed in two steps by the bit icr.csl . the following procedure is recommended to use: ? select the dedicated channel with the multiplexer ? enable the open load current with the dcr.csol bit ? read the dcr.sbm or the standard diagnosis ? disable the open load current with the dcr.csol bit
data sheet 52 rev. 1.0, 2010-04-12 spoc - BTS6460SF diagnosis 9.8 electrical characteristics electrical characteristics diagnosis unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. load current sense 9.8.1 current sense ratio k ilis t j = -40 c channel 0, 1: 0.600 a 1.3 a 2.6 a 4.0 a 7.5 a 2190 3990 4690 5130 5490 5840 6140 6350 6430 6480 50010 12510 9210 8510 7710 ? ? ? ? ? channel 2, 3 (bulb): hwcr.ledn = 0 0.300 a 0.600 a 1.3 a 2.6 a 4.0 a 990 1240 1400 1540 1540 1670 1750 1800 1830 1840 3710 2710 2210 2110 2110 ? ? ? ? ? channel 2, 3 (led): hwcr.ledn = 1 0.050 a 0.150 a 0.300 a 0.600 a 1.0 a 165 300 350 385 400 400 440 450 460 500 1305 675 580 555 555 ? ? ? ? ? 9.8.2 current sense ratio k ilis t j = 25 c to 150 c channel 0, 1: 0.600 a 1.3 a 2.6 a 4.0 a 7.5 a 3120 4420 5030 5130 5490 5840 6140 6350 6430 6480 10960 10010 8660 8240 7710 ? ? ? ? ? channel 2, 3 (bulb): hwcr.ledn = 0 0.300 a 0.600 a 1.3 a 2.6 a 4.0 a 990 1240 1400 1540 1540 1670 1750 1800 1830 1840 2690 2300 2100 2110 2110 ? ? ? ? ? channel 2, 3 (led): hwcr.ledn = 1 0.050 a 0.150 a 0.300 a 0.600 a 1.0 a 165 300 350 385 400 400 440 450 460 500 805 640 580 555 555 ? ? ? ? ?
spoc - BTS6460SF diagnosis data sheet 53 rev. 1.0, 2010-04-12 9.8.3 current sense drift of unaffected channel during inverse current of other channels channel 0, 1 channel 2, 3 (bulb) channel 2, 3 (led) ? k ilis(ic) -20 % -20 % -20 % -20 % -20 % -20 % ? ? ? ? ? ? 20 % 20 % 20 % 20 % 20 % 20 % 1) dcr.mux 111 i l0, 1 = 7.5 a i l1, 0 (ic) = 7.5 a i l2, 3 (ic) = 2.6 a hwcr.ledn = 0 i l2, 3 = 2.6 a i l0, 1 (ic) = 7.5 a i l3, 2 (ic) = 2.6 a hwcr.ledn = 1 i l2, 3 = 0.6 a i l0, 1 (ic) = 7.5 a i l3, 2 (ic) = 2.6 a 9.8.4 current sense voltage limitation v is(lim) 0.9 v dd v dd 1.1 v dd v dcr.mux = 011 i l3 = 2 a r is = 2.7 k ? 9.8.5 maximum steady state current sense output current i is(max) 5.5 ? ? ma 1) v is = 0 v 9.8.6 current sense leakage / offset current channel 0, 1 channel 2, 3 i is(en) ? ? ? ? 76 76 a i l = 0 a dcr.mux 111 9.8.7 current sense leakage, while diagnosis disabled i is(dis) ??1 a dcr.mux = 110 9.8.8 current sense settling time after channel activation channel 0, 1 t sis(on) ??150 s v bb = 13.5 v r is = 2.7 k ? r l = 2.2 ? channel 2, 3 ? ? ? ? 150 100 hwcr.ledn = 0 r l = 6.8 ? hwcr.ledn = 1 r l = 33 ? 9.8.9 current sense desettling time after channel deactivation t dis(off) ? ? ? ? 25 25 s 1) v bb = 13.5 v r is = 2.7 k ? hwcr.ledn = 0 hwcr.ledn = 1 9.8.10 current sense settling time after change of load current channel 0, 1 t sis(lc) ??30 s 1) v bb = 13.5 v r is = 2.7 k ? i l = 7.5 a to 4.0 a channel 2, 3 ? ? ? ? 30 30 hwcr.ledn = 0 i l = 2.6 a to 1.3 a hwcr.ledn = 1 i l = 0.6 a to 0.3 a electrical characteristics diagnosis (cont?d) unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
data sheet 54 rev. 1.0, 2010-04-12 spoc - BTS6460SF diagnosis 9.8.11 current sense settling time after current sense activation t sis(en) ??25 s r is = 2.7 k ? dcr.mux : 110 -> 000 9.8.12 current sense settling time after multiplexer channel change t sis(mux) ??30 s r is = 2.7 k ? r l0 = 2.2 ? r l2 = 33 ? dcr.mux : 010 -> 000 9.8.13 current sense deactivation time t dis(mux) ??25 s 1) r is = 2.7 k ? dcr.mux : 000 -> 110 switch bypass monitor 9.8.14 switch bypass monitor threshold v ds(sb) 1.5 ? 4 v ? open load in off current source 9.8.15 current source in off-state i l(ol) 100 3.0 ? ? 450 7.5 a ma iecr.csl = 0 iecr.csl = 1 current sense synchronization signal 9.8.16 l level signal voltage v issy(l) 0?0.4v i issy = -0.5 ma 9.8.17 h level signal voltage v issy(h) v dd - 0.4 v ? v dd v 1) i issy = 0.5 ma v dd = 4.3 v 9.8.18 signal enable time t issy(en) ??4 s 1) c l = 20 pf 9.8.19 signal disable time t issy(dis) ??4 s 1) c l = 20 pf 1) not subject to production test, specified by design. electrical characteristics diagnosis (cont?d) unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spoc - BTS6460SF diagnosis data sheet 55 rev. 1.0, 2010-04-12 9.9 command description dcr diagnosis control register w/r rb addr 9876543210 read 1 0 0 1 1 0 0 0 0 0 amux sbm mux write 1 0 0 1 1 0 0 0 0 0amuxcsol mux output state out.outn field bits type description 0 (off-state) mux 2:0 r/w set current sense multiplexer configuration 000 is pin is high impedance 001 is pin is high impedance 010 is pin is high impedance 011 is pin is high impedance 100 is pin is high impedance 101 is pin is high impedance 110 is pin is high impedance 111 stand-by mode (is pin is high impedance) sbm 3 r switch bypass monitor 1) 0 v ds < v ds(sb) 1 v ds > v ds(sb) 1) invalid in stand-by mode 1 (on-state) mux 2:0 r/w set current sense multiplexer configuration 000 current sense of channel 0 is routed to is pin 001 current sense of channel 1 is routed to is pin 010 current sense of channel 2 is routed to is pin 011 current sense of channel 3 is routed to is pin 100 is pin is high impedance 101 is pin is high impedance 110 is pin is high impedance 111 stand-by mode (is pin is high impedance)) sbm 3 r switch bypass monitor 1) 0 v ds < v ds(sb) 1 v ds > v ds(sb) field bits type description csol 3 w current source switch fo r open load detection 0 off 1on amux 4 rw automatic current sense multiplexer switching during automatic pwm generation 0 off 1on
data sheet 56 rev. 1.0, 2010-04-12 spoc - BTS6460SF diagnosis chcrn channel configuration register w/r rb addr 9876543210 r/w110xx 0 0 0 phsn sydeln freqn field bits type description sydeln n = 0 to 3 3:2 rw delay of current sense synchronization signal for channel n 00 no synchronization signal delay 01 synchronization signal delay 1: 8 / ( f pclk (or f int )) 10 synchronization signal delay 2: 16 / ( f pclk (or f int )) 11 synchronization signal delay 3: 24 / ( f pclk (or f int )) standard diagnosis cs 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 ter 0 lhi sbm x cle x x x x x x x err3 err2 err1 err0 field bits type description errn n = 3 to 0 nr error flag channel n 0 normal operation 1 failure mode occurred sbm 13 r switch bypass monitor 1) 0 v ds < v ds(sb) 1 v ds > v ds(sb) 1) invalid in stand-by mode
spoc - BTS6460SF diagnosis data sheet 57 rev. 1.0, 2010-04-12 icr inputand current source configuration register w/r rb addr 9876543210 r/w10001 0 0 0 0 0 0 col incg csl 0 field bits type description csl 1 rw level for current source for open load detection 0 low level 1 high level
data sheet 58 rev. 1.0, 2010-04-12 spoc - BTS6460SF serial peripheral interface (spi) 10 serial peripheral interface (spi) the serial peripheral interface (spi) is a full duplex sync hronous serial slave interface, which uses four lines: so, si, sclk and cs . data is transferred by the lines si and so at the rate given by sclk. the falling edge of cs indicates the beginning of an access. da ta is sampled in on line si at the falling edge of sclk and shifted out on line so at the rising edge of sclk. each access must be terminated by a rising edge of cs . a modulo 8 counter ensures that data is taken only, when a multiple of 8 bit has been transferred, while the minimum of 16 bit is also taken into consideration. therefor e the interface provides daisy chain capability even with 8 bit spi devices. figure 25 serial peripheral interface 10.1 spi signal description cs - chip select: the system micro controller selects the spoc - BTS6460SF by means of the cs pin. whenever the pin is in low state, data transfer can take place. when cs is in high state, any signals at the sclk and si pins are ignored and so is forced into a high impedance state. cs high to low transition: ? the requested information is transferred into the shift register. ? so changes from high impedance state to high or lo w state depending on the logi c or combination between the transmission error flag ( ter ) and the signal level at pin si. as a re sult, even in daisy chain configuration, a high signal indicates a faulty transmission. this inform ation stays available to the first rising edge of sclk. figure 26 combinatorial logic for ter flag cs low to high transition: ? command decoding is only done, when after the falling edge of cs exactly a multiple (1, 2, 3, ?) of eight sclk signals have been detected. in case of faul ty transmission, the transmission error flag ( ter ) is set and the command is ignored. ? data from shift register is transferred into the addressed register. 14 13 12 11 14 13 12 11 msb msb spi _16bit . emf lsb 6 5 4 3 2 1 lsb 6 5 4 3 2 1 10 9 8 10 9 8 7 7 so si cs sclk time ter.emf si spi or ter 0 1 so cs sclk s so s si
spoc - BTS6460SF serial peripheral interface (spi) data sheet 59 rev. 1.0, 2010-04-12 sclk - serial clock: this input pin clocks the in ternal shift register. the serial input (si) transfers da ta into the shift register on the falling edge of sclk while the serial output (s o) shifts diagnostic information out on the rising edge of the serial clock. it is essential that the sclk pin is in low state whenever chip select cs makes any transition. si - serial input: serial input data bits are shift-in at this pin, the most significant bit first. si information is read on the falling edge of sclk. the input data consists of two parts, co ntrol bits followed by data bits. please refer to section 10.5 for further information. so serial output: data is shifted out serially at this pin, the most significant bit first. so is in high impedance state until the cs pin goes to low state. new data will appear at the so pi n following the rising edge of sclk. please refer to section 10.5 for further information. 10.2 daisy chain capability the spi of spoc - BTS6460SF provides daisy chain capability. in this configuration se veral devices are activated by the same cs signal mcs . the si line of one device is connecte d with the so line of another device (see figure 27 ), in order to build a chain. the ends of the chain are connected with the output and input of the master device, mo and mi respectively. the ma ster device provides the master cl ock mclk which is connected to the sclk line of each device in the chain. figure 27 daisy chain configuration in the spi block of each device, there is one shift register where one bit from si line is shifted in each sclk. the bit shifted out occurs at the so pin. after eight sclk cyc les, the data transfer for one device has been finished. in single chip configuration, the cs line must turn high to make the devic e accept the transferred data. in daisy chain configuration, the data shifted out at device 1 ha s been shifted in to device 2. when using three devices in daisy chain, three times 16 (or e.g. 16 + 8 +16) bits ha ve to be shifted through the devices. after that, the mcs line must turn high (see figure 28 ). si device 1 spi sclk so cs si device 2 spi sclk so cs si device 3 spi sclk so cs mo mi mcs mclk spi _daisychain . emf
data sheet 60 rev. 1.0, 2010-04-12 spoc - BTS6460SF serial peripheral interface (spi) figure 28 data transfer in daisy chain configuration 10.3 timing diagrams figure 29 timing diagram spi access mi mo mcs mclk si device 1 si device 2 si device 3 so device 1 so device 2 so device 3 time spi_daisychain2_16bit .emf cs sclk si t cs(lead) t cs( td ) t cs( l a g ) t scl k( h) t scl k( l ) t scl k( p) t si( su ) t si( h ) so t so( v) t so( e n ) t so( d is) 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd 0. 7 v dd 0. 2 v dd spi t iming. emf
spoc - BTS6460SF serial peripheral interface (spi) data sheet 61 rev. 1.0, 2010-04-12 10.4 electrical characteristics electrical characteristics seri al peripheral interface (spi) unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max. input characteristics (cs , sclk, si) 10.4.1 l level of pin cs sclk si v cs(l) v sclk(l) v si(l) 0 ? 0.2* v dd v v dd = 4.3 v 10.4.2 h level of pin cs sclk si v cs(h) v sclk(h) v si(h) 0.4* v dd ? v dd v v dd = 4.3 v 10.4.3 pull-up resistor at cs pin r cs 50 120 180 k ? i cs = 100 a 10.4.4 pull-down resistor at pin sclk si r sclk r si 50 120 180 k ? ? i sclk = 100 a i si = 100 a output characteristics (so) 10.4.5 l level output voltage v so(l) 0?0.4v i so = -0.5 ma 10.4.6 h level output voltage v so(h) v dd - 0.4 v ? v dd v i so = 0.5 ma v dd = 4.3 v 10.4.7 output tristate leakage current i so(off) -10 ? 10 a v cs = v dd timings 10.4.8 serial clock frequency f sclk 0 0 ? ? 5 3 mhz 1) v dd = 4.3 v 2) v dd = 3.0 v 10.4.9 serial clock period t sclk(p) 200 333 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 10.4.10 s e r i a l c l o c k h i g h t i m e t sclk(h) 100 166 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 10.4.11 serial clock low time t sclk(l) 100 166 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 10.4.12 enable lead time (falling cs to rising sclk) t cs(lead) 200 333 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 10.4.13 enable lag time (falling sclk to rising cs ) t cs(lag) 200 333 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 10.4.14 transfer delay time (rising cs to falling cs ) t cs(td) 200 333 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 10.4.15 data setup time (required time si to falling sclk) t si(su) 20 33 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v 10.4.16 data hold time (falling sclk to si) t si(h) 20 33 ? ? ? ? ns 1) v dd = 4.3 v 2) v dd = 3.0 v
data sheet 62 rev. 1.0, 2010-04-12 spoc - BTS6460SF serial peripheral interface (spi) 10.4.17 output enable time (falling cs to so valid) t so(en) ? ? ? ? 200 333 ns 2) c l = 20 pf v dd = 4.3 v v dd = 3.0 v 10.4.18 output disable time (rising cs to so tri-state) t so(dis) ? ? ? ? 200 333 ns 2) c l = 20 pf v dd = 4.3 v v dd = 3.0 v 10.4.19 output data valid time with capacitive load t so(v) ? ? ? ? 100 166 ns 2) c l = 20 pf v dd = 4.3 v v dd = 3.0 v 1) not subject to production test, specified by design. spi functional test is performed at f sclk = 5 mhz. 2) not subject to production test, specified by design. electrical characteristics seri al peripheral interface (spi) (cont?d) unless otherwise specified: v bb = 8 v to 17 v, v dd = 3.0 v to 5.5 v, t j = -40 c to +150 c typical values: v bb = 13.5 v, v dd = 4.3 v, t j = 25 c pos. parameter symbol limit values unit test conditions min. typ. max.
spoc - BTS6460SF serial peripheral interface (spi) data sheet 63 rev. 1.0, 2010-04-12 10.5 spi protocol 16bit note: reading a register needs two spi frames. in the first frame the rd command is sent. in the second frame the output at spi signal so will cont ain the requested information. a ne w command can be executed in the second frame. the standard diagnosis can be access ed either by sending the standard diagnosis read command or it is transmitted after each write command. cs 1) 1) the so pin shows this information between cs hi -> lo and first sclk lo -> hi transition. 1514131211109876543210 write out register si 100000000000out3out2out1out0 read out register si 000000xxxxxxxxx0 write configuration an d control registers si 1 x addr data read configuration and control registers si 0x addr xxxxxxxxx0 read standard diagnosis si 0xxxxxxxxxxxxxx1 standard diagnosis soter0lhisbmxclexxxxxxxerr3err2err1err0 second frame of read command so ter 1 0 0 0 0 0 x x x x x x out3 out2 out1 out0 so ter 1 x addr data field bits type description w/r 15 w 0 read 1write rb 14 rw register bank 0 read / write to register bank 0 1 read / write to register bank 1 ter cs r transmission error 0 previous transmission was successf ul (modulo 16 clocks received) 1 previous transmission failed or first transmission after reset outn n = 3 to 0 nw output control register of channel n 0 off 1on addr 13:10 rw address pointer to register for read and write command data 9:0 rw data data written to or read from register selected by address addr errn n = 3 to 0 nr diagnosis of channel n 0 no failure 1 over temperature, over load or short circuit
data sheet 64 rev. 1.0, 2010-04-12 spoc - BTS6460SF serial peripheral interface (spi) cle 11 r external clock status 1) 0 f pclk > f pclk(th) 1 f pclk < f pclk(th) sbm 13 r switch bypass monitor 1) 0 v ds < v ds(sb) 1 v ds > v ds(sb) lhi 14 r limp home enable 2) 0 h-input signal at pin lhi 1 l-input signal at pin lhi 1) invalid in stand-by mode 2) not latching information, read of lhi-status during falling cs field bits type description
spoc - BTS6460SF serial peripheral interface (spi) data sheet 65 rev. 1.0, 2010-04-12 10.6 register overview register bank 0 note: a readout of an u nused register will return the standard diagnosis. register bank 1 bit 151413121110 9 8 7 6 5 4 3 2 1 0 name w/r rb addr data out w/r00000000000out3out2out1out0 pcr w/r 0 0 1 1 1 0 0 0 0 0 0 dcs dpsh pst dccr0 w/r 0 1 0 0 0 0 dc0 dccr1 w/r 0 1 0 0 1 0 dc1 dccr2 w/r 0 1 0 1 0 0 dc2 dccr3 w/r 0 1 0 1 1 0 dc3 field bits type description rb 6 - read bit 0 read / write to register bank 0 1 read / write to register bank 1 addr 5:4 w address pointer to register for read and write command data 3:0 rw data data written to or read from register selected by address addr outn n = 3 to 0 nrw set output mode for channel n 0 channel n is switched off 1 channel n is switched on pst 0 rw automatic pwm generation 0 no automatic pwm generation 1 automatic pwm generation dpsh 6:4 rw device phase shift 00 no phase shift 01 phase shift 1: 8 / ( f pclk (or f int )) 10 phase shift 2: 16 / ( f pclk (or f int )) 11 phase shift 3: 24 / ( f pclk (or f int )) dcs 0 rw single duty cycle for all channels 0 duty cycle setting of channel 0 used for all channels 1 individual duty cycle setting used for each channel dcn n = 0 to 8:0 rw duty cycle for channel n during automatic pwm generation 000000000 dc value: 0 (channel off) 000000001 dc value: (1 / 256) * 100 000000010 dc value: (2 / 256) * 100 ... 011111111 dc value: (255 / 256) * 100 1xxxxxxxx dc value: 1 (channel 100% on)
data sheet 66 rev. 1.0, 2010-04-12 spoc - BTS6460SF serial peripheral interface (spi) note: a readout of an u nused register will return the standard diagnosis. bit 151413121110 9 8 7 6 5 4 3 2 1 0 name w/r rb addr data icr w/r10001000000colincgcsl0 hwcr r 1 0 0 1 0 0 clktrim clk 0 led3 led2 stb cl w 1 0 0 1 0 0 clktrim clk 0 led3 led2 rst cl dcr r1001100000 amux sbm mux w1001100000 amux csol mux chcr0w/r11000000 psh0 sydel0freq0 chcr1w/r11001000 psh1 sydel1freq1 chcr2w/r11010000 psh2 sydel2freq2 chcr3w/r11011000 psh3 sydel3freq3 field bits type description csl 1 rw level for current source for open load detection 0 low level 1 high level incg 2 rw input drive configuration 0 direct drive mode 1 assigned drive mode col 3 rw input combinatorial logic configuration 0 input signal or-combined with according out register bit 1 input signal and-combined with according out register bit cl 0 rw clear latch 0 thermal and over current latches are untouched 1 command: clear all thermal and over current latches rst 1 w reset command 0 normal operation 1 execute reset command stb 1 r standby mode 0 device is awake 1 device is in standby mode ledn n = 3 to 2 nrw set led mode for channel n 0 channel n is in bulb mode 1 channel n is in led mode clk 5 rw clock mode 1) 0 external clock input pclk is used for pwm mode 1 internal clock is used for pwm mode
spoc - BTS6460SF serial peripheral interface (spi) data sheet 67 rev. 1.0, 2010-04-12 clktrim 8:6 rw internal clock trim 000 f int - 4 k trim ... 011 f int - 1 k trim 100 f int without trimming 101 f int + 1 k trim ... 111 f int + 3 k trim mux 2:0 rw set current sense multiplexer configuration in off-state 000 is pin is high impedance 001 is pin is high impedance 010 is pin is high impedance 011 is pin is high impedance 100 is pin is high impedance 101 is pin is high impedance 110 is pin is high impedance 111 stand-by mode (is pin is high impedance) set multiplexer config uration in on-state 000 current sense of channel 0 is routed to is pin 001 current sense of channel 1 is routed to is pin 010 current sense of channel 2 is routed to is pin 011 current sense of channel 3 is routed to is pin 100 is pin is high impedance 101 is pin is high impedance 110 is pin is high impedance 111 stand-by mode (is pin is high impedance)) sbm 3 r switch bypass monitor 2) 0 v ds < v ds(sb) 1 v ds > v ds(sb) csol 3 w current source switch for open load detection 0 off 1on amux 5:4 w automatic current sense multip lexer switching (single loop) 0 automatic current se nse multiplexer switching not activated 1 automatic current sense multiplexer switching activated and proceeding freqn n = 0 to 3 1:0 rw pwm frequency prescaler setting for channel n 00 normal mode without automatic pwm generation 01 prescaler 1: f pclk (or f int ) / 256 10 prescaler 2: f pclk (or f int ) / 512 11 prescaler 4: f pclk (or f int ) / 1024 sydeln n = 0 to 3 3:2 rw delay of current sense synchronization signal for channel n 00 no synchronization signal delay 01 synchronization signal delay 1: 8 / ( f pclk (or f int )) 10 synchronization signal delay 2: 16 / ( f pclk (or f int )) 11 synchronization signal delay 3: 24 / ( f pclk (or f int )) field bits type description
data sheet 68 rev. 1.0, 2010-04-12 spoc - BTS6460SF serial peripheral interface (spi) pshn n = 0 to 3 6:4 rw channel phase shift for channel n 000 no phase shift 001 phase shift 1: 32/ ( f pclk (or f int )) 010 phase shift 2: 64 / ( f pclk (or f int )) ... 110 phase shift 6: 192 / ( f pclk (or f int )) 111 phase shift 7: 224 / ( f pclk (or f int )) 1) for avoiding skews it is recommended to change from external to internal clock source or vice versa only during deactivated pwm generator ( pcr.pst = 0 b ). 2) invalid in stand-by mode field bits type description
spoc - BTS6460SF application description data sheet 69 rev. 1.0, 2010-04-12 11 application description figure 30 application circuit example 1 spi vbb out3 out2 out1 out0 65 w 65 w 27 w 10 w issy so sclk si cs gnd vdd gnd circuit_pwm.emf vdd 100nf c e.g. xc2267 vss vcc v bat ad 3.9k ? 3.9k ? 5v 500 ? 2.7k ? 1k ? 1nf spi pwm generator pclk 3.9k ? gpio 3.9k ? 3.9k ? 8k ? 8k ? gpio gpio in2 in3 in1 wd-out 10 ? 2 lhi is 3.9k ? gpio 1 for filtering and protection purposes 2 for increased iso-pulse robustness 68nf wd-out 8k ? 10k ?
data sheet 70 rev. 1.0, 2010-04-12 spoc - BTS6460SF package outlines spoc - BTS6460SF 12 package outlines spoc - BTS6460SF figure 31 pg-dso-36-43 (plastic dual small outline package) green product (rohs compliant) to meet the world-wide customer requirements for environmentally friendly products and to be compliant with government regulations the device is available as a green product. green products are rohs-compliant (i.e pb-free finish on leads and suitable for pb-free soldering according to ipc/jedec j-std-020). gps01089 2) does not include dambar protrusion of 0.05 max. per side 1) does not include plastic or metal protrusion of 0.15 max. per side 1 18 36 19 0.65 0.33 0.2 2.45 2.65 max. 0.1 -0.2 -0.1 0.23 +0.09 0.35 x 45? -0.2 1) 7.6 10.3 0.7 ?.2 8? max. ?.3 index marking 1) 12.8 -0.2 18 1 19 36 index marking ejector mark bottom view 0.17 m c a-b d 36x ?.08 2) c d a b dimensions in mm you can find all of our packages, sorts of pa cking and others in our infineon internet page ?products?: http://www.infineon.com/products .
spoc - BTS6460SF revision history data sheet 71 rev. 1.0, 2010-04-12 13 revision history revision date changes 1.0 2010-04-12 initial data sheet
edition 2010-04-12 published by infineon technologies ag 81726 munich, germany ? 2010 infineon technologies ag all rights reserved. legal disclaimer the information given in this docu ment shall in no event be regarded as a guarantee of conditions or characteristics. with respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, infine on technologies hereby disclaims any and all warranties and liabilities of any kind, including witho ut limitation, warranties of non-infrin gement of intellectua l property rights of any third party. information for further information on technology, delivery terms and conditions and prices, please contact the nearest infineon technologies office ( www.infineon.com ). warnings due to technical requirements, components may contain dangerous substances. for information on the types in question, please contact the nearest infineon technologies office. infineon technologies compon ents may be used in life-su pport devices or systems only with the express written approval of infineon technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system or to affect the safe ty or effectiveness of that de vice or system. life support devices or systems are intended to be implanted in the hu man body or to support an d/or maintain and sustain and/or protect human life. if they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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